Delay Analysis of MAC
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چکیده
This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed MAC accumulates the intermediate results in thetype of sum and carry bits instead of the output of the final adder, which made it feasible to optimize the pipeline scheme to improve the performance. Based on the theoretical estimation, we analyzed the results of delay. We expect that the proposed MAC can be modified to different fields requiring high performance such as the signal processing areas. Keywords— Booth multiplier, carry save adder (CSA) tree, computer arithmetic, digital signal processing (DSP), multiplierand-accumulator (MAC), modified booth algorithm(MBA), two’s complement, parallel multiplier ,carry look-ahead adder (CLA),Baugh–Wooley algorithm (BWA),Booth algorithm (BA).
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